A phase-locked loop (PLL) is a control system that generates a signal having a fixed phase relationship to a reference signal. PLLs are widely used in radio, telecommunications, computers and other electronic applications. They may be used to generate stable frequencies, recover a signal from a noisy communication channel, or distribute clock timing pulses in digital logic designs such as microprocessors. FIG. 1 depicts a typical PLL 100 with a common-mode-logic-to-CMOS (CML-to-CMOS) converter. The PLL 100 compares a reference signal Fref with a divided version of the clock signal Fdivided and adjusts the output VCO 108 based on the results of the comparison so that the clock signal Fclock maintains a fixed phase relationship with the reference signal Fref.
At the output stage of a typical PLL circuit, a common-mode-logic-to-CMOS (CML-to-CMOS) converter 110 is required to convert the CML differential voltage levels to CMOS compatible voltage levels. CML voltage levels represent the two values of a data bit depending on which of the two levels is higher than the other. In contrast, a typical CMOS circuit operates according to a single ended signal with two pre-determined voltage levels defining the two values of transmitted data bits.
In high frequency PLLs used for clock applications in Application Specific Integrated Circuits (ASICs), it is difficult to maintain the duty cycle specification of the output clock of the PLL. Some applications require a tight specification for a duty cycle of 45-55%. As small geometries are used in the PLL circuit to achieve frequencies of up to 1 GHz, the mismatch between transistors and the mismatch in input signals causes increased spread in the duty cycle of the output clock. Therefore, it is desired to improve the circuit design of the CML-to-CMOS converter to achieve a duty cycle substantially equal to 50% in the output clock signal.